ETRI Develops World’s First Chip Packing Tech Capable of Reducing Power by 95%
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ETRI Develops World’s First Chip Packing Tech Capable of Reducing Power by 95%
Its process has been reduced from the conventional eight stages to three; nano new material has been developed

23(Sat), Sep, 2023




President Bang Seung-chan of Electronics and Telecommunications Research Institute (ETRI).


A Korean research team has come close to achieving a major milestone in the semiconductor industry by developing a new material, a core part in the packaging sector, essential for the development of advanced semiconductors. 

The technology is predicted to be used as a core material technology for the production of high-performance AI chips, such as self-driving vehicles and in data centers.

The Electronics and Telecommunications Research Institute (ETRI) has developed a new material essential for a semiconductor process using its own nano material technology for the first time in the world. 




A view of a dramatic semiconductor chiplet packaging technology that can reduce power consumption 95 percent compared to Japan’s own technology. (Photos: ETRI) 


The breakthrough is a dramatic semiconductor chiplet packaging technology that can reduce power consumption 95 percent compared to Japan’s best technology. 

The process has been reduced from the conventional eight stages to three. 

The semiconductor chiplet packaging technology has a three-step process of applying a new material called “non-conductive film (NCF) on a wafer, irradiating cotton laser onto chiplets shaped like tiles and hardening them. 

The semiconductor industry has so far utilized Japanese-made materials in the advanced semiconductor packaging process. 

But the nine-stage process, requiring complex and diverse equipment, has shortcomings, such higher power consumption, higher clean room maintenance costs and harmful substance emission. 

Global chipmakers, such as TSMC, Intel and Samsung Electronics have scrambled to develop new cluster technologies for high-precession chips using nanometer advanced chip systems. 

The conventional technology’s drawbacks include the impossibility of cleaning joints connecting several micrometer chips and in room temperature inosculation, as required by the chiplet integration technology. 

The research team developed on its own the technology after about 20 years of research into core proprietary technology using its own nano design technology and nano new materials. 

The developed process involves the application of the nano new material developed on advanced chip wafer substrates, making tiles with chiplets produced on diverse wafers and a process of joining by irradiating cotton laser for about one second before fishing with a post-hardening process. 

The core new material, developed by the research team, is made with a high-molecule film. It is a polymer film made of epoxy-based substances and a reducing agent, with a thickness ranging from 10 to 20 micrometers.

Irradiating cotton laser in the material can solve the previous stage of cleaning, drying, coating and hardening at the post-semiconductor process of packaging. 

The nano new material, developed by ETRI, has characteristics, such as role of bonding in the post-chip process and each stage material characteristic. 

The conventional process involves chips separated from wafers and applying them to a board, being cut one by one. 

The nano new material has enabled chiplets to be fixed into wafer substrate like placing tiles. 

The technology has reduced the length of its total production line from current 20 meters to four meters by 20 percent. 

The new technology has the strength of emitting no harmful substances, since nitrogen gas is not necessary. 

It is a high-precision process, now available for applying of advanced chiplet packages. 

It is characterized by integrating process at room temperatures (25 degrees in Centigrade) for the first time for the development of a high-precession process. 

The conventional process, requiring each stage temperature to 100 degrees in Centigrade, causes problems, such as power consumption, error increase and declining reliability due to thermal expansion. 

The research team explained that it developed the new material and new engineering methods for the first time in the world that enable bonding at room temperature sans fume, caused by rising temperatures. 

Not only micro LED startups of the United States but also global foundry makers have been conducting fairness and reliability evaluations of the technology, and if excellent evaluations are made, it is predicted to be commercialized in three years. 

The ETRI research team believes that the technology will offer solutions to low-power and eco-friendly engineering methods semiconductor display companies want. 

It plans to expand the extendibility and usefulness of the technology by applying it to advanced chiplet integration and micro LED transcription and connection processes. 

The research has been implemented under the material innovation leadership project of the Ministry of Science and ICT (MSIT). 

KIST, Korea Institute of Ceramic Engineering & Technology and KITECH are participating in the project as joint research institutes. 

   
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